1. Technical Field
The present inventive concept relates to non volatile memory (NVM) devices, and Single Root Input/output Virtualization (SR-IOV), and more particularly relates to an NVM device that allows distribution of queue resources supported by the NVM device across virtual and/or physical functions.
2. Discussion of Related Art
To fulfill the increasing requirement of interoperability, lower latency, higher throughput, and lower computation overhead, the Peripheral Component Interconnect (PCI) Special Interest Group (PCI-SIG) introduced a Single Root I/O Virtualization (SR-IOV) specification, which allows a device to appear to be multiple separate physical PCI express (PCIe) devices. The SR-IOV works through physical functions (PF) and virtual functions (VF). The PF's are full PCIe functions that include the SR-IOV extended capability. The capability is used to configure and manage the SR-IOV functionality. The PF includes all of the extended capabilities in the PCIe based specifications. The VFs are “lightweight” functions that contain the resources necessary for data movement but have a carefully minimized set of configuration resources. The SR-IOV may allow each VM to have direct access to hardware, such as a Network Interface Controller (NIC), a Converged Network Adapter (CAN), or a Host Bus Adapter (HBA), using the virtual function.
An NVM controller generally uses multiple command queues for issuing commands to NVM devices and response queues for receiving responses from NVM devices. With the increase in the number of virtual machines supported by a host system, the number of VFs supported by the device is also expected to increase. Due to this, the total number of queues supported by the device would also increase. However, an NVM controller implements a static number of queues since it is inefficient to implement the hardware logic required to implement the increasing number of the command queues and the response queues.